1. Field of the Invention
The present invention generally relates to a semiconductor device testing apparatus for testing various kinds of semiconductor devices, and more particularly, relates to an improvement in the logical comparison part of a semiconductor device testing apparatus for testing one or more semiconductor integrated circuits (hereinafter referred to as IC or ICs) which are a typical example of semiconductor devices, specifically, one or more IC memories such as a RAM (random access memory), a ROM (read only memory), a charge coupled device (CCD) or the like, as to the quality thereof, that is, whether it is a good (pass) article or a defective (failure) article.
Further, in order to make the understanding of the present invention easier, in the following disclosure the present invention will be described with a case that the present invention is applied to an IC memory testing apparatus for testing one or more IC memories as to whether it is a good (pass) article or a defective (failure) article. However, it is needless to say that the present invention can also be applied to a semiconductor device testing apparatus for testing one or more ICs other than an IC memory or one or more semiconductor devices other than an IC as to whether it is a pass article or a failure article.
2. Description of Related Art
An IC memory testing apparatus comprises, roughly speaking, a timing generator (strobe generator), a pattern generator, a waveform shaping device, a logical comparison circuit, and a failure analysis memory. The pattern generator generates, in response to a reference clock supplied from the timing generator, an address signal, a series of test data signals having a predetermined pattern and a control signal which are to be supplied to an IC memory to be tested (commonly called a device under test (DUT)), and generates an expected value data signal to be supplied to the logical comparison circuit, and the like. The address signal, the test data signal and the control signal are inputted once to the waveform shaping device where those signals are shaped to have the waveforms required for testing an IC memory to be tested, and then are applied to the IC memory to be tested.
An IC memory to be tested is controlled in writing or reading of test data thereinto or therefrom by an application of a control signal thereto. That is, when a control signal for writing is applied to the IC memory to be tested, test data is successively written into addresses of the IC memory to be tested, each address being specified by a corresponding address signal. When a control signal for reading is applied to the IC memory to be tested, written test data is successively read out from addresses of the IC memory to be tested, each address being specified by an address signal.
The read-out data signals read out from the IC memory to be tested are supplied to the logical comparison circuit where each of the read-out data signals is compared with an expected value data signal outputted from the pattern generator. When the comparison result is a discord, the logical comparison circuit outputs a defect signal what is called a failure (or fail) signal indicating the discord. Usually, a logical "1" is outputted as a failure signal. On the contrary, when the comparison result is an accord, the logical comparison circuit outputs a conformable signal what is called a pass signal which indicates the conformity. Since a failure signal is a logical "1", a logical "0" is outputted as a pass signal. A failure signal is sent to a failure analysis memory and is stored therein, but a pass signal is usually not stored in the failure analysis memory.
After the completion of one test cycle, it is decided whether the tested IC memories is pass articles or failure articles, by taking into consideration the number of failure signals, the locations of occurrences of failure signals and the like stored in the failure analysis memory.
An example of a conventional IC testing apparatus of this type for testing an IC memory as to whether it is a pass article or a failure article will be described with reference to FIG. 11 which shows mainly the arrangement of the logical comparison part thereof.
In each of a series of test periods constituting one test cycle, a response signal read out from each terminal (pin) of an IC memory to be tested 1 is supplied first to a corresponding level comparator 2 where its signal level (usually voltage level) is compared with a reference level. There are two reference levels one of which is a reference voltage VOH which is used when an output from an IC memory to be tested is logical "1" and the other of which is a reference voltage VOL which is used when an output from an IC memory to be tested is logical "0". In the illustrated circuit construction, in case the reference voltage VOH is used, a logical "1" is outputted from the level comparator 2 when the comparison result is a pass and a logical "0" is outputted from the level comparator 2 when the comparison result is a failure. In case the reference voltage VOL is used, a logical "0" is outputted from the level comparator 2 when the comparison result is a pass and a logical "1" is outputted from the level comparator 2 when the comparison result is a failure. Although only one circuit construction for one pin of the IC memory 1 is shown in the drawing, the circuit construction for each of other pins is the same as that shown in the drawing.
An output signal V (FIG. 12a) from the level comparator 2 is supplied to a logical comparison circuit 5 which is constituted by two logical comparator circuits 5a and 5b. The output signal V is branched into two parts one of which is supplied to the logical comparator circuit 5a and the other of which is supplied to the logical comparator circuit 5b. Both the logical comparator circuits 5a and 5b have the same circuit arrangement and comprise latch circuits 3a and 3b and exclusive OR (XOR) gates 4a and 4b, respectively. An output signal V from the level comparator 2 is supplied to both the latch circuits 3a and 3b of the respective logical comparator circuits 5a and 5b. Strobe signals Sa and Sb (FIGS. 12b and 12c) having the same frequency (for example, 100 MHz) and phases different from each other respectively are supplied from the strobe generator (timing generator) 6 to clock terminals of these latch circuits 3a and 3b respectively to latch the output signal V from the level comparator 2 into the latch circuits 3a and 3b at the fall time points (edges) of the strobe signals, respectively. That is, the branched output signals V are latched at the fall edges of the strobe signals into the latch circuits 3a and 3b, respectively.
The output signal V from the level comparator 2 is updated for every test period T in one test cycle. Each test period T is equal to the period of each of the strobe signals Sa and Sb. Assuming that the frequency of each strobe signal is fs, the test period T is equal to 1/fs, namely, T=1/fs.
The output signals of the latch circuits 3a and 3b are inputted to one input terminals of the corresponding exclusive OR gates 4a and 4b of the logical comparator circuits 5a and 5b respectively where they are logically compared with expected value data signals Ea and Eb outputted from the pattern generator, respectively. Since the expected value data signals Ea and Eb are ones which have the same logic as that of the test data signal applied to the IC memory 1 to be tested, in case that an output from the IC memory 1 to be tested is to be a logical "1", the expected value data signals Ea and Eb inputted respectively to the other terminals of the XOR gates 4a and 4b are logical "1". Also, in case that an output from the IC memory 1 to be tested is to be a logical "0", the expected value data signals Ea and Eb inputted respectively to the other terminals of the XOR gates 4a and 4b are logical "0". Thus, in case that a logical "1" signal is inputted to the latch circuits 3a and 3b from the level comparator 2 when an output from the IC memory 1 to be tested is to be a logical "1", this logical "1" signal coincides with the expected value data signal (logical "1"). As a result, logical "0" signals, i.e., pass signals are generated from the XOR gates 3a and 3b, respectively. Whereas, when a logical "0" signal is inputted to the latch circuits 3a and 3b, this logical "0" signal does not coincide with the expected value data signal (logical "1"). As a result, logical "1" signals, i.e., failure signals Fa and Fb are generated from the XOR gates 4a and 4b, respectively.
On the other hand, in case that a logical "0" signal is inputted to the latch circuits 3a and 3b from the level comparator 2 when an output from the IC memory 1 to be tested is to be a logical "0", this logical "0" signal coincides with the expected value data signal (logical "0"). As a result, logical "0" signals, i.e., pass signals are generated from the XOR gates 3a and 3b, respectively. Whereas, when a logical "1" signal is inputted to the latch circuits 3a and 3b, this logical "1" signal does not coincide with the expected value data signal (logical "0"). As a result, logical "1" signals, i.e., failure signals Fa and Fb are generated from the XOR gates 4a and 4b, respectively.
These failure signals Fa and Fb are inputted to a failure selection circuit 7 where one of the failure signals Fa and Fb is selected to be written in corresponding one of the failure analysis memories 8a and 8b, or both the failure signals Fa and Fb are written in the corresponding failure analysis memories 8a and 8b, respectively.
As discussed above, the logical comparison part of the conventional IC memory testing apparatus uses only one strobe generator (timing generator) 6 to logically compare the signal level of a response signal read out from each of the terminals of the IC memory 1 to be tested with an expected value data signal at one or two time points (one or two timings) in each test period T of one test cycle, thereby to determine whether the IC memory to be tested is a pass article or a failure article. In such case, since the frequency of a strobe signal depends upon the performance (for example, 100 MHz) of the strobe generator, it cannot be possible to generate a strobe signal having a frequency beyond the performance of the strobe generator. Therefore, it has been impossible in the conventional IC memory testing apparatus to test an IC memory which operates at a high speed (for example, 200 MHz or 400 MHz) beyond the performance of the strobe generator and to determine whether it is a pass article or a failure article.
In addition, in case that, for example, the performance of a DRAM (dynamic RAM) is required to be classified into four categories with respect to the access time thereof, two test cycles are needed to perform such classification in the above-mentioned conventional IC memory testing apparatus because only two systems of strobe signals are available. Consequently, there is a disadvantage in the conventional IC memory testing apparatus that it takes a longer time to perform the classifying operation.
The above problems also occur in a semiconductor device testing apparatus for testing one or more ICs other than an IC memory or one or more semiconductor devices other than an IC as to whether it is a pass article or a failure article if the semiconductor device testing apparatus is provided with a logical comparison part the circuit arrangement of which is similar to that of the conventional IC memory testing apparatus.
Moreover, a request or demand has been recently increased for a semiconductor device testing apparatus that a semiconductor device testing apparatus is available in which each test period in one test cycle and a timing for logical comparison can be variously changed so that all of semiconductor devices from low speed semiconductor devices operating at a low speed to high speed semiconductor devices operating at a high speed can be tested regarding their various performances by only one semiconductor device testing apparatus.